From silicon transistors and logic gates to the Von Neumann architecture and the Fetch-Decode-Execute cycle.
Deconstruct the Von Neumann model: CPU, Main Memory, System Buses (Address, Data, Control), and I/O.
Trace the Fetch-Decode-Execute cycle through hardware registers (PC, MAR, MDR, CIR, ACC).
Compare access latencies across Registers, L1/L2/L3 Cache, RAM, NVMe Flash, and Secondary Storage.
Build half-adders from logic gates (AND, OR, NOT, XOR) and explore the OS kernel layer.
In 1804, Joseph Marie Jacquard created a weaving loom controlled by punched cards. In 1945, John von Neumann realized program instructions and data could both be stored electronically in the exact same memory.
Before stored-program computers, reprogramming ENIAC meant physically rewiring patch cables and switchboards for days. Today, a modern Apple M3 or Intel Core chip packs over 25 billion transistors into a silicon wafer the size of a postage stamp!
A computer is a programmable electronic device that accepts raw data (input), performs high-speed logical/arithmetic operations, and generates output according to stored instructions.
If a system can simulate any single-taped Turing machine (perform any computable algorithm given time and memory), it is Turing Complete.
Unlike a mechanical clock or fixed microwave timer, a computer's behavior is defined entirely by software loaded into memory.
Computers maintain mutable state across cycles, allowing loops, conditional branches, and persistent file modification.
Every computational system operates around this fundamental pipeline:
Keyboard, mouse, camera, microphone, temperature sensor, network packets.
ALU performs arithmetic and boolean logic; CU coordinates instruction flow.
Primary (RAM/Cache) holds active instructions; Secondary (SSD) stores long-term state.
Display monitor (OLED/LCD), speakers, motor actuators, network responses.
The primary execution engine. Reads bytecode, performs calculations, and directs data traffic.
Volatile, high-speed primary memory holding currently executing programs and datasets.
Massively parallel processor with thousands of cores optimized for vector/matrix math and 3D graphics.
Non-volatile NAND flash memory storing the OS, files, and installed software when powered off.
Printed circuit board (PCB) providing high-speed copper traces (PCIe, SATA) connecting all components.
Converts AC wall current into regulated DC voltages (+12V, +5V, +3.3V) for delicate microcircuits.
Proposed in 1945, this architectural model remains the foundation of 99% of general-purpose computers today.
Both program instructions (code) and data (variables) reside in the same physical addressable memory space. The CPU fetches instructions and data over shared system buses.
A single CPU core is comprised of four cooperative functional units:
Directs the operations of the processor. It fetches instructions, decodes opcodes into micro-operations, and generates electrical control pulses.
The mathematical calculator. Performs integer arithmetic (+, -, *, /) and bitwise boolean logic (AND, OR, XOR, NOT).
Extremely small, ultra-fast internal SRAM storage cells that hold data being operated on in the current clock cycle.
On-chip L1/L2 cache SRAM that buffers recently accessed instructions and data to avoid waiting for slow main RAM.
Holds the memory address of the next instruction to be fetched from RAM. Automatically increments after each fetch.
Holds the physical RAM address currently being read from or written to via the Address Bus.
Holds the actual data word or instruction recently fetched from RAM, or waiting to be written to RAM.
Holds the instruction opcode and operand currently being decoded by the Control Unit.
Stores the intermediate output and computational results of the most recent ALU operation.
How the CPU retrieves the next instruction from memory:
Address in Program Counter is copied into the Memory Address Register.
MAR asserts address across Address Bus; CU sends a Memory Read signal.
RAM copies instruction word over Data Bus into the Memory Data Register.
Instruction copied to CIR. Program Counter increments by 1 word size.
The Control Unit decodes the raw binary instruction in the CIR into hardware control signals:
The Control Unit's internal instruction decoder looks up the Opcode in the CPU's Instruction Set Architecture (ISA) table and routes power lines to the ALU and register gates.
The CPU executes the operation requested by the instruction:
Data from address 0x0F is fetched into MDR and added to the Accumulator: ACC = ACC + MDR.
If the instruction is a conditional jump (e.g. JMP 0x20), the Program Counter is updated directly to change execution flow.
Results stored back into destination register or written to RAM via MAR/MDR write cycle.
The CPU master clock quartz oscillator synchronizes all transistor switching events.
A 4.0 GHz CPU pulses 4,000,000,000 times per second. 1 clock cycle takes just 0.25 nanoseconds!
Modern CPUs overlap execution stages like an assembly line: while Instruction 3 is being executed, Instruction 2 is being decoded, and Instruction 1 is being fetched simultaneously.
Computers cannot have memory that is simultaneously infinite, instantaneous, and cheap. We use a hierarchy:
Size: ~1 KB
Latency: 0.5 ns
On-chip flip-flops
Size: 32 KB - 64 MB
Latency: 1 - 10 ns
SRAM on silicon
Size: 16 - 64 GB
Latency: 60 - 80 ns
DRAM modules
Size: 1 - 4 TB
Latency: 25,000 ns
Non-volatile NAND
Silicon transistors act as microscopic electronic switches with two stable states: Voltage High (1) or Voltage Low (0).
A single binary digit (0 or 1). Represents 2 states ($2^1$).
8 bits. Represents $2^8 = 256$ distinct values (ASCII characters, RGB color channels: 0-255).
Modern CPUs process 64 bits (8 bytes) in a single clock cycle, addressing up to $2^{64} \approx 18$ Exabytes of RAM.
By wiring CMOS transistors together, we build fundamental logic circuits:
Inverts the input voltage signal.
Outputs 1 only if both inputs are 1.
Outputs 1 if at least one input is 1.
Outputs 1 if inputs are different; outputs 0 if inputs are identical.
A NAND gate (NOT AND) is functionally complete. Any digital circuit, ALU, or supercomputer CPU in existence can be constructed entirely using only interconnected NAND gates!
How does a CPU calculate $1 + 1 = 2$ in binary ($1 + 1 = 10_2$)?
A XOR B (Outputs 0 when $1+1$, outputs 1 when $1+0$).A AND B (Outputs 1 when $1+1$, representing the carry over).Different processors understand different native machine language vocabularies (ISAs):
Complex Instruction Set Computer: Instructions can perform multi-step memory operations directly. Dominates desktop PCs, gaming rigs, and enterprise cloud servers.
Reduced Instruction Set Computer: Simple, fixed-length instructions that execute in single cycles. High energy efficiency; powers all smartphones, tablets, and modern MacBooks.
Silicon transistors, buses, RAM, registers.
UEFI / BIOS initializes hardware on power-on.
Privileged scheduler managing RAM and CPU time.
Python scripts, web browsers, Discord, games.
Time-slices CPU cores across hundreds of background threads using preemptive multitasking.
Gives every app an isolated virtual address space, paging unused memory pages to SSD swap when RAM fills.
Translates generic OS requests (e.g. write(data)) into specific hardware commands for graphics cards or Wi-Fi chips.
"A 64-core CPU at 5.0 GHz will always run every game and Python script 8 times faster than an 8-core CPU."
Amdahl's Law: Performance gain from parallel computing is strictly limited by the portion of the program that is serial. If a game physics engine or Python script runs on 1 thread, 63 extra cores sit completely idle!
1. NVMe M.2 Flash Drive → [Secondary Storage (Non-Volatile)]
2. Control Unit (CU) → [CPU Instruction Coordination]
3. OLED 144Hz Screen → [Output Subsystem]
4. L1 Cache SRAM → [High-Speed Primary Memory]
5. ALU → [Arithmetic & Logic Processing]
A modern CPU can calculate instructions in 0.25 nanoseconds. But fetching data from main RAM across the motherboard bus takes 70 nanoseconds.
The CPU spends over 95% of its potential cycles sitting stalled (idle), waiting for data to arrive from memory.
How do modern chip designers (Intel, AMD, Apple) combat this bottleneck? (Hint: Think about cache hierarchies, branch prediction, and prefetching!)
If 1 CPU clock cycle (0.3 ns) were scaled up to equal 1 second in human time:
1 ns = 3 seconds
(Reaching into your pocket)
70 ns = 4 minutes
(Walking down the hall)
25,000 ns = 1 day
(Waiting for next-day delivery)
50 ms = 5.2 years
(Attending high school + college)
CPU: Intel Core i9-14900K (24 cores, 6.0 GHz)
GPU: NVIDIA RTX 4090 (24GB VRAM)
RAM: 4GB DDR4 Single Channel (2133 MHz)
Primary Drive: 5400 RPM Mechanical Magnetic HDD (SATA)
PSU: 450W Generic Power Supply
Unified memory for code and data connected to CPU via Address, Data, and Control buses.
Continuous cycle: Fetch via PC/MAR/MDR → Decode in CIR/CU → Execute via ALU & Registers.
Tradeoff between speed and cost: Registers → SRAM Cache → DRAM RAM → Flash SSD.
Transistors → Logic Gates → Adders/ALU → CPU Cores → OS Kernel → High-Level Software.
In 3 sentences, describe what happens from the moment you press the 'A' key on your keyboard to the moment 'A' appears on your monitor:
1. Hardware interrupt signal sent via USB controller to OS kernel.
2. OS context-switches CPU to text editor process; updates memory buffer in RAM.
3. GPU renders font glyph from RAM buffer into frame buffer; sends HDMI signal to OLED pixels!